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COMe-P2020 User Guide
62
Table 3-48: 0x309: Default eTSEC2 Protocol Configuration Register (Reserved, See note!)
ACTION D7 D6 D5 D4 D3 D2 D1 D0
READ NU NU NU NU NU NU cfg_tsec2_prto[0:1]
WRITENUNUNUNUNUNU NU
POWER UP1111111 1
BITFIELD DESCRIPTION
[D0-D1] 00 Reserved
01 The eTSEC2 controller operates using the MII protocol (or RMII if
configured in reduced mode if not configured to operate in SGMII mode.
10 The eTSEC2 controller operates using the GMII protocol (or RGMII if
configured in reduced mode if not configured to operate in SGMII mode.
11 The eTSEC2 controller operates using the TBI protocol (or RTBI if
configured in reduced mode if not configured to operate in SGMII mode.
N O T I C E
Equivalent CPU strapping is hard coded in CPLD depends on board variant, read value is always 0xFC.
Table 3-49: 0x30A: Default eTSEC3 Protocol Configuration Register (Reserved, See note!)
ACTION D7 D6 D5 D4 D3 D2 D1 D0
READ NU NU NU NU NU NU cfg_tsec2_prto[0:1]
WRITENUNUNUNUNUNU NU
POWER UP1111111 1
BITFIELD DESCRIPTION
[D0-D1] 00 Reserved
01 The eTSEC3 controller operates using the RMII protocol if not configured
to operate in SGMII mode.
10 The eTSEC3 controller operates using the RGMII protocol if not
configured to operate in SGMII mode.
11 The eTSEC3 controller operates using the RTBI protocol if not configured
to operate in SGMII mode (default).
N O T I C E
Equivalent CPU strapping is hard coded in CPLD depends on board variant, read value is always 0xFC.
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