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COMe-P2020 User Guide
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2 Functional Description
2.1 Processor
The COMe-cP2020 supports the high-performance, 32-bit, 45nm dual-core Freescale QorIQ P2020 processor with the fol-
lowing functions and features:
• Two e500v2 cores built on Power Architecture technology, running up to 1.2 GHz clock speed
• 512 Kbyte shared level two cache
• One 64-bit DDR3 SDRAM memory controllers with ECC and chip-select interleaving support
• Data path acceleration architecture incorporating acceleration for Packet-/Buffer- and Queue-Management
• Three 1 Gbps Ethernet controllers
• Up to three PCI Express 1.0a controllers/ports running at 2.5 Gbps
• Two serial RapidIO controllers/ports version 1.2 running at up to 3.125 Gbps
• One ULPI controller
• One SD/MMC controller
• One SPI controller
• Two I2C controllers
• Two DUARTs
• One enhanced local bus controller
• Multicore programmable interrupt controller
2.2 Memory
2.2.1 DDR3
The COMe-cP2020 supports a soldered, single-channel (72-bit), Double Data Rate (DDR3) memory with Error Checking and
Correcting (ECC) running at up to 800 MHz (memory error detection and reporting of 1-bit and 2-bit errors and correction
of 1-bit failures). The available memory configuration can be either 1 GB, 2 GB or 4 GB.
2.2.2 Flash Memory
2.2.2.1 SPI Boot Flash
The COMe-cP2020 provides two 2 MB SPI boot flashes for two separate U-Boot images, a standard SPI boot flash and a
recovery SPI boot flash. The fail-over mechanism for the U-Boot recovery can be controlled via the DIP switch SW1, switch
1. Refer to Chapter 6.10 for further information.
The SPI boot flashes include a hardware write protection option. If write protection is enabled, writing to the SPI boot
flashes is not possible.
N O T I C E
The U-Boot code and settings are stored in the SPI boot flashes. Changes made to the U-Boot set-
tings are available only in the currently selected SPI boot flash. Thus, switching over to the other
SPI boot flash may result in operation with different U-Boot code and settings.
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