Kontron COMe-cHL6 Instrukcja Użytkownika Strona 57
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COMe-cHL6 / Pinout List
A65 PCIE_TX1- PCI Express lane 1 - Transmit DP-O - -
A66 GND Power Ground PWR - -
A67 GPI2 EXT_GPI2 / General Purpose Input 2 I-3.3 PU 10k 3.3V (S0) -
A68 PCIE_TX0+ PCI Express lane 0 + Transmit DP-O - -
A69 PCIE_TX0- PCI Express lane 0 - Transmit DP-O - -
A70 GND Power Ground PWR - -
A71 LVDS_A0+/eDP_TX2+ LVDS_A_DATA0_P / eDP_TX2_P DP-O - -
A72 LVDS_A0-/eDP_TX2- LVDS_A_DATA0_N / eDP_TX2_N DP-O - -
A73 LVDS_A1+/eDP_TX1+ LVDS_A_DATA1_P / eDP_TX1_P DP-O - -
A74 LVDS_A1-/eDP_TX1- LVDS_A_DATA1_N / eDP_TX1_N DP-O - -
A75 LVDS_A2+/eDP_TX0+ LVDS_A_DATA2_P / eDP_TX0_P DP-O - -
A76 LVDS_A2-/eDP_TX0- LVDS_A_DATA2_N / eDP_TX0_N DP-O - -
A77 LVDS/eDP_VDD_EN LVDS/eDP_VDD_EN / LVDS/eDP Panel Power
Control
O-3.3 PD 100k -
A78 LVDS_A3+ LVDS_A_DATA3_P / LVDS Channel A Data3+ DP-O - -
A79 LVDS_A3- LVDS_A_DATA3_N / LVDS Channel A Data3- DP-O - -
A80 GND Power Ground PWR - -
A81 LVDS_A_CK+/eDP_TX3+ LVDS_A_CLK_P / eDP_TX3_P / LVDS Ch A Clock+ DP-O - -
A82 LVDS_A_CK-/eDP_TX3- LVDS_A_CLK_N / eDP_TX3_N / LVDS Ch A Clock- DP-O - -
A83 LVDS_I2C_CK/eDP_AUX+ LVDS_DDC_CLK / eDP_AUX_P / LVDS I2C Clock I/O-3.3 PU 2k21 3.3V (S0) -
A84 LVDS_I2C_DAT/eDP_AUX- LVDS_DDC_DATA / eDP_AUX_N / LVDS I2C Data I/O-3.3 PU 2k21 3.3V (S0) -
A85 GPI3 EXT_GPI3 / General Purpose Input 3 I-3.3 PU 10k 3.3V (S0) strapping function (if pulled low till release of
CB_RESET#, LVDS is disabled to enable eDP)
A86 RSVD n.c. Nc - -
A87 RSVD/eDP_HPD n.c. / eDP Hot Plug Detect DP-0 - -
A88 PCIE_CLK_REF+ CLK_PCIE_REF_P / PCIE Reference Clock DP-O - -
A89 PCIE_CLK_REF- CLK_PCIE_REF_N / PCIE Reference Clock DP-O - -
A90 GND Power Ground PWR - -
A91 SPI_POWER V3.3_SPI_POWER O-3.3 - power supply pin for external SPI flash
A92 SPI_MISO SPI_SO / SPI slave output I-3.3 - int. PU 20k in PCH
A93 GPO0 EXT_GPO0 / General Purpose Output 0 O-3.3 PD 10k -
A94 SPI_CLK SPI_CLK / SPI clock O-3.3 - -
A95 SPI_MOSI SPI_SI / SPI slave input O-3.3 - int. PD 20k in PCH
A96 TPM_PP TPM Physical Presence I-3.3 PD 100k -
A97 TYPE10# n.c. for type 2 module Nc - -
A98 SER0_TX serial port 0 TXD O-3.3 - -
A99 SER0_RX serial port 0 RXD I-3.3 PU 47K 3.3V (S0) -
A100 GND Power Ground PWR - -
A101 SER1_TX serial port 1 TXD O-3.3 - -
A102 SER1_RX serial port 1 RXD I-3.3 PU 47K 3.3V (S0) -
A103 LID# LID switch input I-3.3 PU 10K 3.3V (S5) -
A104 VCC_12V main input voltage (8.5-20V) PWR 8.5-20V - -
A105 VCC_12V main input voltage (8.5-20V) PWR 8.5-20V - -
A106 VCC_12V main input voltage (8.5-20V) PWR 8.5-20V - -
A107 VCC_12V main input voltage (8.5-20V) PWR 8.5-20V - -
A108 VCC_12V main input voltage (8.5-20V) PWR 8.5-20V - -
A109 VCC_12V main input voltage (8.5-20V) PWR 8.5-20V - -
A110 GND Power Ground PWR - -
57
- COMe-cHL6 1
- » Table of Contents « 3
- 1 User Information 5
- 1.5 Warranty 6
- 1.6 Technical Support 6
- 2 Introduction 7
- 2.2 Naming clarification 8
- 2.5 COM Express® Benefits 9
- 3 Product Specification 10
- 3.2 Functional Specification 11
- Graphics Core 15
- Connectivity 16
- Misc Interfaces and Features 17
- Kontron Features 17
- Additional features 17
- Power Features 17
- 3.3 Block Diagram 18
- 3.4 Accessories 19
- 3.5 Electrical Specification 20
- 3.5.5 ATX Mode 21
- 3.5.6 Single Supply Mode 21
- 3.6 Power Control 22
- 3.7.2 Humidity 23
- WEEE Directive 24
- Conformal Coating 24
- Shock & Vibration 25
- 3.9 MTBF 26
- 3.10 Mechanical Specification 27
- 3.11 Module Dimensions 28
- 4 Features and Interfaces 30
- 4.4 SPI boot 32
- Using an external SPI flash 33
- 4.5 M.A.R.S 34
- 4.6 UART 35
- 4.7 Fast I2C 36
- Time-out events 37
- WDT Signal 37
- 4.10 Speedstep Technology 40
- 4.11 C-States 41
- 4.12 Hyper Threading 42
- 4.14 Display Configuration 44
- DDI Design Consideration 46
- DVI-I Design Topology 46
- Requirements 47
- Setup a Multi-monitor system 47
- 4.16 Intel® vPro™ technology 48
- 5 System Resources 50
- 5.2 Memory Area 51
- 5.3 I/O Address Map 51
- 5.5 Internal I2C Bus 52
- 5.6 External I2C Bus 52
- 6 Connectors 54
- 7 Pinout List 55
- 7.2 Connector X1A Row A 56
- COMe-cHL6 / Pinout List 57
- 7.3 Connector X1A Row B 58
- 7.4 Connector X1B Row C 60
- 7.5 Connector X1B Row D 62
- 8 BIOS Operation 64
- 8.4 Setup Guide 65
- 8.5 BIOS Setup 66
- System Information 67
- Boot Features 68
- Network Stack 70
- Platform Information 71
- 8.5.2 Advanced 72
- Silicon Information 73
- Processor Configuration 74
- Processor Power Management 75
- Miscellaneous 77
- I2C Speed 78
- Watchdog 79
- Generic LPC Decode Ranges 80
- H/W Monitor 81
- HDD Configuration 83
- Memory Configuration 86
- Graphics Configuration 89
- IGD Configuration 90
- South Bridge Configuration 92
- SB PCI Express Config 93
- PCI Express Root Port 1/2/3/4 94
- SB USB Config 95
- SB Azalia Config 96
- Network Configuration 97
- CPLD Configuration 98
- LPC SIO Configuration 99
- ME Configuration 100
- Thermal Configuration 101
- CPU Thermal Configuration 102
- COMe-cHL6 / BIOS Operation 103
- Passive Cooling 104
- ICC Configuration 105
- Intel® Rapid Start Technology 107
- 8.5.3 Security 109
- Security 110
- 8.5.4 Boot 111
- 8.5.5 Exit 112
- Corporate Offices 113
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