Kontron COMe-bPC2 Instrukcja Użytkownika Pobierz pdf (Strona 35)

COMe-bPC2 / Features and Interfaces

4.5 Fast I2C

The COMe-bPC2 supports a CPLD implemented LPC to I2C bridge using the WISHBONE I2C Master Core provided from

opencores.org. The I2C Interface supports transfer rates up to 40kB/s and can be configured in Setup

Specification for external I2C:

» Speed up to 400kHz

» Compatible to Philips I2C bus standard

» Multi-Master capable

» Clock stretching support and wait state generation

» Interrupt or bit-polling driven byte-by-byte data-transfers

» Arbitration lost interrupt with automatic transfer cancellation

» Start/Stop signal generation/detection

» Bus busy detection

» 7bit and 10bit addressing

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COMe-bPC2 1
» Table of Contents « 3
1 User Information 6
1.5 Warranty 7
1.6 Technical Support 7
2 Introduction 8
COMe-bPC2 / Introduction 9
2.5 COM Express® Benefits 10
3 Product Specification 11
Accessories 12
3.2 Functional Specification 13
GMCH and IOH specifications 14
Graphics Core 15
Connectivity 16
Misc Interfaces and Features 16
Kontron Features 16
Power Features 17
Supported Operating Systems 17
3.3 Block Diagram 18
3.4 Electrical Specification 19
3.4.5 ATX Mode 20
3.4.6 Single Supply Mode 20
3.5 Power Control 21
3.6.2 Humidity 22
CE marking 23
WEEE Directive 23
Conformal Coating 23
Shock & Vibration 24
3.8 MTBF 25
3.9 Mechanical Specification 26
3.10 Module Dimensions 26
3.10.2 38009-XXXX-XX-X 27
3.11 Thermal Management 28
3.12 Heatspreader 28
3.13 Onboard Fan Connector 29
4 Features and Interfaces 31
4.3 LPC boot 33
4.4 M.A.R.S 34
4.5 Fast I2C 35
4.6 JIDA16 and JIDA32 36
4.7 K-Station 1 37
4.8.1 I2C 38
4.8.2 Storage 38
4.8.3 GPIO 38
4.8.4 Hardware Monitor 38
Configuration 39
4.10 Watchdog Timer 40
4.11 Flash Backup Feature 41
4.12 Speedstep Technology 43
4.13 C-States 44
4.15 VID-x 46
4.20 Display Configurations 50
DDI Design Consideration 51
Requirements 52
Setup a Multi-monitor system 52
4.22 Intel® vPro™ technology 54
5 System Ressources 56
5.1.2 In APIC mode 57
COMe-bPC2 / System Ressources 58
6 Connectors 59
7 Pinout List 60
7.2 Connector X1A Row A 61
COMe-bPC2 / Pinout List 62
7.3 Connector X1A Row B 63
7.4 Connector X1B Row C 65
7.5 Connector X1B Row D 67
8 BIOS Operation 69
8.3 Setup Guide 70
8.4 BIOS Setup 72
8.4.2 Module Info 73
Module Software Revisions 74
Current LVDS Configuration 74
Memory Module Information 75
8.4.3 Advanced Menu 76
CPU Configuration 77
IDE Configuration 78
IDE Device Submenu 79
AHCI Configuration 80
AHCI PortN Submenu 81
SuperIO Configuration 82
Floppy Configuration Submenu 83
ACPI Configuration 84
ACPI Cooling Options 85
PCIExpress Configuration 87
USB Configuration 88
COMe-bPC2 / BIOS Operation 89
Hardware Health 90
Baseboard Hardware Health 92
Miscellaneous Settings 93
Event Log Configuration 94
MARS Interface Configuration 95
Watchdog 96
I2C Busses 97
Remote Access Configuration 98
Ethernet Configuration 99
Features 100
ME Subsystem Configuration 101
Intel VT-d Configuration 102
Trusted Computing 103
8.4.4 PCIPnP Menu 104
8.4.5 Boot 105
Boot Setting Configuration 106
8.4.6 Security 107
8.4.7 Chipset 108
North Bridge Configuration 109
Display Control 110
Internal LVDS Configuration 111
Southbridge Configuration 112
LPC Decode Range 113
8.4.8 Exit Menu 114
Corporate Offices 115

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